In the semiconductor production industry, various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include the deposition of layers of different materials including metallization layers, passivation layers and insulation layers on the wafer substrate, as well as photoresist stripping and sidewall passivation polymer layer removal. In modern memory devices, for example, multiple layers of metal conductors are required for providing a multi-layer metal interconnection structure in defining a circuit on the wafer. Chemical vapor deposition (CVD) processes are widely used to form layers of materials on a semiconductor wafer. Other processing steps in the fabrication of the circuits include formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked pattern; removing the mask layer using reactive plasma and chlorine gas, thereby exposing the top surface of the metal interconnect layer; cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate; and removing or stripping polymer residues from the wafer substrate.
After the devices are fabricated on the wafer surface, the wafers are packaged and transported to a separate facility which is remote from the fabrication facility for separation of the wafers into individual chips. The integrated circuits on the wafer are prone to damage due to mechanical shock during transit from the fabrication facility to the packaging or other facility. In addition to mechanical shock, integrated circuits are susceptible to damage by electrostatic discharges (ESD) and electrical overstress (EOS). As USLI technology continues downscaling of device features, the wafer size becomes correspondingly larger for economical production of the integrated circuits. Accordingly, the wafers become increasingly expensive with increased size. For example, the cost of a 12″ wafer is about 2.5 times the cost of an 8″ wafer. One production lot (25 wafers) of 8″ wafers costs about $40,000. Thus, protection of the wafers during shipping is of utmost importance. Clearly, suppliers of semiconductor wafers would, if possible, like to avoid or reduce as much as possible the potential wafer damage, inconvenience and quality control issues which are associated with traditional methods of packaging wafers for transport.
Transport and storage of semiconductor wafers has presented problems as the diameter of wafers has increased in size and the circuitry on the wafers has become increasingly miniaturized. Containers for storing and transporting IC wafers are described in U.S. Pat. Nos. 4,787,508 and 5,366,079. While the disclosed containers are major improvements over other known containers, in certain situations, damage can still occur. The large-diameter wafers (8 or 12 inches in diameter) are the most vulnerable to damage. Any movement of or stress on the wafers in the container could potentially damage the very fragile circuit patterns on the surface of the wafers and/or crack the wafers.
U.S. Pat. No. 5,366,079 discloses a container and retainer combination that effectively reduces damage due to shifting of the wafers in the container. However, the storage and handling of very large diameter wafers still presents problems due to the flexing of the large diameter containers when they are opened and otherwise manipulated, resulting in fractured and broken wafers.
A typical conventional IC (integrated circuit) wafer container, such as that disclosed in U.S. Pat. No. 5,699,916, is shown in FIGS. 1 and 2. The wafer container 8 includes a wafer holder 12 including a base 14 with a stepped wafer support surface 16 thereon. Multiple, curved or arcuate wafer panels 18 extend upwardly from the wafer support surface 16, defining a vertical slot 20 between adjacent wafer panels 18. As shown in FIG. 2, multiple semiconductor wafers 22 are stacked on the wafer support surface 16 and on each other. An enclosure 10 fits over the upward-standing wafer panels 18 and the wafer support surface 16 and engages the base 14 to enclose the stacked wafers 22.
Removal or unpacking of the individual wafers 22 from the wafer holder 12 is effected by extending an elongated vacuum pin 24, terminated by a vacuum head 25, through one of the slots 20 and then applying the vacuum head 25 to the upper surface of the uppermost wafer 22 such that vacuum pressure holds the wafer 22 against the vacuum head 25. Next, the vacuum pin 24 and attached wafer 22 are lifted, as indicated by the arrows, until the wafer 22 being removed clears the height of the wafer panels 18. The wafer 22 is then moved horizontally over the wafer panels 18 and placed in a separate location.
One of the problems commonly encountered during unpacking of the wafers 22 from the wafer holder 12 is that the delicate wafers 22, horizontal movement of which is constrained by the fixed wafer panels 18, may be damaged in the event that the wafers 22 inadvertently collide with the wafer panels 18 during removal. For that reason, much care must be taken to minimize horizontal movement of the vacuum pin 24 and the wafer 22 being removed to prevent collision of the wafer 22 with the wafer panels 18. Consequently, unloading of all of the wafers 22 from the wafer holder 12 may require an inordinately long period of time, reducing the operational efficiency of the unpacking procedure. Accordingly, a wafer container is needed which facilitates removal or unpacking of wafers in an efficient and safe manner.
An object of the present invention is to provide a new and improved wafer container suitable for IC (integrated circuit) wafers.
Another object of the present invention is to provide a new and improved wafer container suitable for storing and/or transporting IC wafers, which container facilitates the efficient and safe removal of IC wafers from the container.
Still another object of the present invention is to provide a new and improved wafer container which enables horizontal as well as vertical removal of IC wafers from the container.
Yet another object of the present invention is to provide a new and improved wafer container which prevents cracking, chipping or other damage to IC wafers as the wafers are unpacked or removed from the container.
A still further object of the present invention is to provide a new and improved wafer container which includes a wafer holder having multiple, upward-standing sidewalls, at least one of which may be removed to enable horizontal removal of IC wafers from the container.
Yet another object of the present invention is to provide a new and improved wafer container including a wafer holder having multiple, upward-standing sidewalls, the inner surface of which sidewalls may be fitted or coated with a soft flexible material or pad to prevent scratching of the wafers during wafer storage, transport and/or removal.